A 10 Gb/s CMOS clock and data recovery circuit with frequency detection

@article{Savoj2001A1G,
  title={A 10 Gb/s CMOS clock and data recovery circuit with frequency detection},
  author={Jafar Savoj and B.. Razavi},
  journal={2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177)},
  year={2001},
  pages={78-79}
}
A 10 Gb/s phase-locked clock and data recovery circuit incorporates a multiphase LC oscillator and a half-rate phase/frequency detector with automatic data retiming. In 0.18 /spl mu/m CMOS technology, the circuit exhibits 1.43 GHz capture range and 0.8 ps rms jitter with length 2/sup 23/ PRBS. The power dissipation is 91 mW from a 1.8 V supply. 

Citations

Publications citing this paper.
SHOWING 1-10 OF 21 CITATIONS

References

Publications referenced by this paper.

Similar Papers

Loading similar papers…