A 10 Gb/s 2-IIR-tap DFE receiver with 35 dB loss compensation in 65-nm CMOS

@article{Elhadidy2013A1G,
  title={A 10 Gb/s 2-IIR-tap DFE receiver with 35 dB loss compensation in 65-nm CMOS},
  author={Osama Elhadidy and Samuel Palermo},
  journal={2013 Symposium on VLSI Circuits},
  year={2013},
  pages={C272-C273}
}
A serial I/O receiver efficiently implements a decision feedback equalizer (DFE) employing 2 IIR taps for improved long-tail ISI cancellation. The use of a modified multi-input two-stage slicer allows for both DFE summation to be performed directly at the slicer and optimization of the first-tap IIR filter/mux feedback path to allow for cancellation of the critical first post-cursor. Fabricated in GP 65-nm CMOS, the receiver occupies 0.0304 mm2 area and consumes 9.9 mW while operating at a BER… CONTINUE READING