A 1.8-V 22-mW 10-bit 30-MS/s Pipelined CMOS ADC for Low-Power Subsampling Applications

@article{Li2008A12,
  title={A 1.8-V 22-mW 10-bit 30-MS/s Pipelined CMOS ADC for Low-Power Subsampling Applications},
  author={Jian Li and Xiaoyang Zeng and Lei Xie and Jun Hua Chen and Jianyun Zhang and Yawei Guo},
  journal={IEEE Journal of Solid-State Circuits},
  year={2008},
  volume={43},
  pages={321-329}
}
This paper describes a 10-bit 30-MS/s subsampling pipelined analog-to-digital converter (ADC) that is implemented in a 0.18 mum CMOS process. The ADC adopts a power efficient amplifier sharing architecture in which additional switches are introduced to reduce the crosstalk between the two opamp-sharing successive stages. A new configuration is used in the first stage of the ADC to avoid using a dedicated sample-and-hold amplifier (SHA) circuit at the input and to avoid the matching requirement… CONTINUE READING
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