A 1.4 GHz differential low-noise CMOS frequency synthesizer using a wideband PLL architecture

@article{Lin2000A1G,
  title={A 1.4 GHz differential low-noise CMOS frequency synthesizer using a wideband PLL architecture},
  author={Li Lin and Luns Tee and P. M. D. Gray},
  journal={2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056)},
  year={2000},
  pages={204-205}
}
The growing importance of wireless media for voice and data communications is driving a need for higher integration in personal communications transceivers to achieve lower cost, smaller form factor, and lower power dissipation. One approach to this problem is to integrate the RF functionality in low-cost CMOS technology together with the baseband transceiver functions. This in turn requires integration of the frequency synthesizer with enough isolation from supply noise to allow it to coexist… CONTINUE READING
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