A 1.35V 4.3GB/s 1Gb LPDDR2 DRAM with controllable repeater and on-the-fly power-cut scheme for low-power and high-speed mobile application

@article{Jeong2009A14,
  title={A 1.35V 4.3GB/s 1Gb LPDDR2 DRAM with controllable repeater and on-the-fly power-cut scheme for low-power and high-speed mobile application},
  author={Bong Hwa Jeong and Jongwon Lee and Yin Jae Lee and Tae Jin Kang and Joo Hyeon Lee and Duck Hwa Hong and Jae Hoon Kim and Eun Ryeong Lee and Min Chang Kim and Kyung Ha Lee and Sang Il Park and Jong Ho Son and Sang Kwon Lee and Seong Nyuh Yoo and Sung Mook Kim and Tae Woo Kwon and Jin-Hong Ahn and Yong Tak Kim},
  journal={2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers},
  year={2009},
  pages={132-133}
}
With the advent of high-performance multi-processing demands for real-time multimedia and broadband networking in battery-based mobile systems, high-speed and low power mobile SDRAM/DDRs are becoming increasingly important. We present an on-the-fly power-cut scheme that can be applied to mobile DRAM without any special modes and a global data-line repeater scheme to reduce the data-line delay. In addition, 4b data prefetch and a ZQ calibrated output driver scheme are used to achieve 4.3GB/s… CONTINUE READING

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