• DOI:10.1109/VLSIC.2008.4585996
Corpus ID: 41951338

A 1.3-mW per-channel 103-dB SNR stereo audio DAC with class-D head-phones amplifier in 65nm CMOS

@article{Lee2008A1P,
  title={A 1.3-mW per-channel 103-dB SNR stereo audio DAC with class-D head-phones amplifier in 65nm CMOS},
  author={Y. Lee and Chun-Kyun Seok and Bong-Joo Kim and Seung-Bin You and Wang-Seup Yeum and Ho-Jin Park and Y. Jun and B. Kong and Jae-Whui Kim},
  journal={2008 IEEE Symposium on VLSI Circuits},
  year={2008},
  pages={176-177}
}

Y. Lee, Chun-Kyun Seok, +6 authors Jae-Whui Kim

Published 2008

Computer Science

2008 IEEE Symposium on VLSI Circuits

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The stereo audio DAC with novel single-ended class-D amplifier achieving a 103-dB SNR is fully integrated in a 65 nm CMOS technology. Novel asymmetric pulse-width modulation (PWM) is applied to minimize switching noise and nonlinearity in the class-D amplifier. The adjustable delta-sigma modulator is also used to suppress supply-voltage modulation. All the functions needed for portable audio playback are implemented in a 0.53-mm2 area dissipating only 1.3-mW per channel from a 2.5-V supply.