A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking

@article{Kim2011A11,
  title={A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking},
  author={Jung-Sik Kim and Chi Sung Oh and Hocheol Lee and Donghyuk Lee and Hyong-Ryol Hwang and Sooman Hwang and Byongwook Na and Joungwook Moon and Jin-Guk Kim and Hanna Park and Jang-Woo Ryu and Kiwon Park and Sanghee Kang and So-Young Kim and Hoyoung Kim and Jong-Min Bang and Hyunyoon Cho and Minsoo Jang and Cheolmin Han and Jung-Bae Lee and Kyehyun Kyung and Joo-Sun Choi and Young-Hyun Jun},
  journal={2011 IEEE International Solid-State Circuits Conference},
  year={2011},
  pages={496-498}
}
  • Jung-Sik Kim, C. Oh, +20 authors Y. Jun
  • Published 2011
  • Computer Science
  • 2011 IEEE International Solid-State Circuits Conference
Mobile DRAM is widely employed in portable electronic devices due to its feature of low power consumption. Recently, as the market trend renders integration of various features in one chip, mobile DRAM is required to have not only low power consumption but also high capacity and high speed. To attain these goals in mobile DRAM, we designed a 1Gb single data rate (SDR) Wide-I/O mobile SDRAM with 4 channels and 512 DQ pins, featuring 12.8GB/s data bandwidth. 
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References

SHOWING 1-10 OF 11 REFERENCES
A 1.35V 4.3GB/s 1Gb LPDDR2 DRAM with controllable repeater and on-the-fly power-cut scheme for low-power and high-speed mobile application
  • B. Jeong, Jongwon Lee, +15 authors Yong Kim
  • Engineering, Computer Science
    2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers
  • 2009
TLDR
An on-the-fly power-cut scheme that can be applied to mobile DRAM without any special modes and a global data-line repeater scheme to reduce the data- line delay is presented.
8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology
TLDR
An 8 Gb 4-stack 3-D DDR3 DRAM with through-Si-via is presented which overcomes the limits of conventional modules and the proposed TSV check and repair scheme can increase the assembly yield up to 98%.
Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register
TLDR
A dual-period self- Refresh (DPS-refresh) scheme for low-power DRAM's is proposed, which can be extended by four to six times compared to the conventional self-Refresh period.
A 300-MHz 25-/spl mu/A/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor
TLDR
An on-chip 1-Mb SRAM suitable for embedding in the application processor used in mobile cellular phones was developed and uses a subdivisional power-line control (SPC) scheme.
Reducing Energy of DRAM/Flash Memory System by OS-controlled Data Refresh
TLDR
Simulations show that the approach can reduce the DRAM refresh energy by 59-74% and the overall energy of DRAM/flash memory system by 8-24% without increase in the execution.
Block-based multiperiod dynamic memory design for low data-retention power
TLDR
This paper investigates a novel scheme that relies on small refresh blocks and multiple refresh periods to reduce DRAM dissipation by decreasing the number of cells refreshed too often and gives a novel polynomial-time algorithm for computing an optimal set of refresh periods for block-based multiperiod refresh.
Adaptive Self Refresh Scheme for Battery Operated High-Density Mobile DRAM Applications
Self refresh current in modern DRAMs is becoming more difficult problem to handle because the decreasing cell transistor size has a negative effect on the uniformity of capacitor charge. In order to
Through-silicon via and die stacking technologies for microsystems-integration
The highest integration density of microsystems can be obtained using a 3D-stacking approach, where each layer of the stack is realized using a different technology, which may include sensors,
The Test Access Port and Boundary Scan Architecture
In combination with a wheel for a bicycle and the like having an annular rim, a hub rotatable about its axis, and axially offset groups of circumferentially spaced spokes which centrally support the
IEEE Standard Test Access Port and Boundary-Scan Architecture IEEE Standard
  • IEEE Standard Test Access Port and Boundary-Scan Architecture IEEE Standard
  • 1149
...
1
2
...