A 1.2-ns16×16-Bit Binary Multiplier Using High Speed Compressors

Abstract

For higher order multiplications, a huge number of adders or compressors are to be used to perform the partial product addition. We have reduced the number of adders by introducing special kind of adders that are capable to add five/six/seven bits per decade. These adders are called compressors. Binary counter property has been merged with the compressor… (More)

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@inproceedings{Dandapat2012A1B, title={A 1.2-ns16×16-Bit Binary Multiplier Using High Speed Compressors}, author={Abhijit Dandapat and S. Ghosal and P. Sarkar and D. Mukhopadhyay}, year={2012} }