A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme

@article{Sohn2013A1V,
  title={A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme},
  author={Kyomin Sohn and Taesik Na and Indal Song and Yong Shim and Wonil Bae and Sanghee Kang and Dongsu Lee and Hangyun Jung and Seok-Hun Hyun and Hanki Jeoung and Ki Won Lee and Jun-Seok Park and Jongeun Lee and Byunghyun Lee and Inwoo Jun and Juseop Park and Junghwan Park and Hundai Choi and Sanghee Kim and Haeyoung Chung and Young Choi and Dae-Hee Jung and Byungchul Kim and Jung-Hwan Choi and Seong-Jin Jang and Chi-Wook Kim and Jung-Bae Lee and Joo-Sun Choi},
  journal={IEEE Journal of Solid-State Circuits},
  year={2013},
  volume={48},
  pages={168-177}
}
A 1.2 V 4 Gb DDR4 SDRAM is presented in a 30 nm CMOS technology. DDR4 SDRAM is developed to raise memory bandwidth with lower power consumption compared with DDR3 SDRAM. Various functions and circuit techniques are newly adopted to reduce power consumption and secure stable transaction. First, dual error detection scheme is proposed to guarantee the reliability of signals. It is composed of cyclic redundancy check (CRC) for DQ channel and command-address (CA) parity for command and address… CONTINUE READING
Highly Cited
This paper has 26 citations. REVIEW CITATIONS
20 Citations
5 References
Similar Papers

Citations

Publications citing this paper.
Showing 1-10 of 20 extracted citations

References

Publications referenced by this paper.
Showing 1-5 of 5 references

A 7 Gb/s/pin GDDR5 SDRAM with 2.5 ns bank-tobank active time and no bank-group restriction

  • T.-Y. Oh
  • IEEE ISSCC Dig. Tech. Papers, 2010, pp. 434–435.
  • 2010
1 Excerpt

Similar Papers

Loading similar papers…