A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution

@article{Sohn2017A1V,
  title={A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution},
  author={Kyomin Sohn and Won-Joo Yun and Reum Oh and Chi Sung Oh and Seong-Young Seo and Min-Sang Park and Dong-Hak Shin and Won-Chang Jung and Sang-Hoon Shin and Je-Min Ryu and Hye-Seung Yu and Jae-Hun Jung and Hyunui Lee and Seok-Yong Kang and Young-Soo Sohn and Jung Hwan Choi and Yong-Cheol Bae and Seong-Jin Jang and G. Y. Jin},
  journal={IEEE Journal of Solid-State Circuits},
  year={2017},
  volume={52},
  pages={250-260}
}
A 1.2 V 20 nm 307 GB/s high-bandwidth memory (HBM) DRAM is presented to satisfy a high-bandwidth requirement of high-performance computing application. The HBM is composed of buffer die and multiple core dies, and each core die has 8 Gb DRAM cell array with additional 1 Gb ECC array. At-speed wafer level, a u-bump IO test scheme and an adaptive refresh scheme considering temperature distribution are proposed to guarantee test coverage and stable operation in a power-efficient manner. 
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