A 1.1 GHz 12 $\mu$A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

@article{Wang2008A1G,
  title={A 1.1 GHz 12 \$\mu\$A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications},
  author={Yih Wang and Hong Jo Ahn and Uddalak Bhattacharya and Zhanping Chen and T. Coan and Fatih Hamzaoglu and W. M. Hafez and Chia-Hong Jan and Pramod Kolar and S. H. Kulkarni and J. Lin and Yong-Gee Ng and I. Post and Liqiong Wei and Ying Zhang and Kevin Zhang and M. Bohr},
  journal={IEEE Journal of Solid-State Circuits},
  year={2008},
  volume={43},
  pages={172-179}
}
A low-power, high-speed SRAM macro is designed in a 65 nm ultra-low-power (ULP) logic technology for mobile applications. The 65 nm strained silicon technology improves transistor performance/leakage tradeoff, which is essential to achieve fast SRAM access speed at substantially low operating voltage and standby leakage. The 1 Mb SRAM macro features a 0.667 mum2 low-leakage memory cell and can operate over a wide range of supply voltages from 1.2 V to 0.5 V. It achieves operating frequency of 1… CONTINUE READING