A 1.0625-to-14.025Gb/s multimedia transceiver with full-rate source-series-terminated transmit driver and floating-tap decision-feedback equalizer in 40nm CMOS

@article{Quan2011A1M,
  title={A 1.0625-to-14.025Gb/s multimedia transceiver with full-rate source-series-terminated transmit driver and floating-tap decision-feedback equalizer in 40nm CMOS},
  author={Shaolei Quan and Freeman Zhong and Wing Liu and Pervez M. Aziz and Tai Jing and Yikui Dong and Chintan Desai and Hairong Gao and Monica Garcia and Gary Hom and Tony Huynh and Hiroshi Kimura and Ruchi Kothari and Lijun Li and Cathy Liu and Scott Lowrie and Kathy Ling and Amaresh V. Malipatil and Ram Narayan and Tom Prokop and Chaitanya Palusa and Anil Rajashekara and Ashutosh Sinha and Charlie Zhong and Eric Zhang},
  journal={2011 IEEE International Solid-State Circuits Conference},
  year={2011},
  pages={348-350}
}
A robust transceiver designed for NRZ signaling beyond 10Gb/s over long-range physical media (including electrical backplanes, copper cables and optical modules) must contend with significant challenges from insertion loss, crosstalk, and reflection. For inter-symbol interference (ISI) cancellation, half-rate decision-feedback equalizer (DFE) with unrolled first tap [1–3] is widely used to avoid noise amplification and to relax timing for data sampling/feedback. However, tap-unrolling increases… CONTINUE READING
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