A 1 V multi-threshold voltage CMOS DSP with an efficient power management technique for mobile phone application

  title={A 1 V multi-threshold voltage CMOS DSP with an efficient power management technique for mobile phone application},
  author={Shin'ichiro Mutoh and Satoshi Shigematsu and Yasuyuki Matsuya and H. Fukuda and Junzo Yamada},
  journal={1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC},
  • S. Mutoh, S. Shigematsu, J. Yamada
  • Published 8 February 1996
  • Computer Science
  • 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC
A low-power digital signal processor (DSP) is the key component for battery-driven mobile phone equipment since a vast amount of data needs to be processed for multimedia use. Reduced supply voltage is a direct approach to power reduction. This 1 V DSPLSI with 26 MOPS and 1.1 mW/MOPS performance adopts a multi-threshold-voltage CMOS (MTCMOS) technique. A small embedded power-management processor decreases power during waiting periods. 

Figures from this paper

Low-power circuits and technology for wireless digital systems
Circuit techniques for low-power communication systems which exploit the capabilities of advanced CMOS technology are described and described.
A 500 MHz, one volt, 16 by 16 bit multiplier for DSP cores
  • C. Lemonds
  • Computer Science
    VLSI Signal Processing, IX
  • 1996
This paper focuses on a 16 by 16 array multiplier that operates with a one volt power supply at a clock frequency of 500 MHz and is implemented in dual rail domino logic using a 0.25 /spl mu/m multi-threshold CMOS process.
An MTCMOS design methodology and its application to mobile computing
This paper examines the effectiveness of the MTCMOS technology for the Samsung's 0.18?m process, proposes a new special flip-flop which keeps a valid data during the sleep mode, and develops a methodology which takes into account the new design issues related to the M TCMos technology.
Low power digital system design: an overview
  • R. Mehra, S. Malik
  • Engineering
    Proceedings of IEEE TENCON '98. IEEE Region 10 International Conference on Global Connectivity in Energy, Computer, Communication and Control (Cat. No.98CH36229)
  • 1998
The need to reduce the power consumption of the next generation of digital systems is clearly recognized. There are significant research efforts along multiple fronts directed towards this end. This
A 27-MHz/54-MHz 11-mW MPEG-4 video decoder LSI for mobile applications
A very low-power MPEG-4 video decoder LSI for mobile applications is presented and has high reusability because it does not use process-dependent technology such as V/sub DD/-hopping and variable threshold voltages.
A 90-nm Low-Power FPGA for Battery-Powered Applications
The design and implementation of Pika, a low-power FPGA core targeting battery-powered applications that achieves substantial power savings through a series of power optimizations and is compatible with existing commercial design tools.
Dual-threshold voltage techniques for low-power digital circuits
Scaling and power reduction trends in future technologies will cause subthreshold leakage currents to become an increasingly large component of total power dissipation. This paper presents several
A self-controllable voltage level (SVL) circuit and its low-power high-speed CMOS circuit applications
A self-controllable voltage level (SVL) circuit which can supply a maximum dc voltage to an active-load circuit on request or can decrease the dc voltage supplied to a load circuit in standby mode
High-speed low-power logic gates using floating gates
This paper resorts to a circuit technique based on floating gate devices in order to lower the threshold voltage, which allows fast operation of logic gates at a low supply voltage in standard technologies.
Low-Power High-Speed Flip Flops (LPHSFF) are proposed in this paper. They are based on CMOS multi-threshold voltage techniques. High threshold voltage MOSFET transistors are applied on the


A 1-V high-speed MTCMOS circuit scheme for power-down applications
A new MTCMOS concept realises a new circuit scheme to hold data during the power-down period in which the power is not supplied, and a scan register has been developed based on this concept.
A 200 mV self-testing encoder/decoder using Stanford ultra-low-power CMOS
  • J. Burr, J. Shott
  • Engineering
    Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94
  • 1994
A CMOS test chip that includes a 1k-transistor self-testing encoder/decoder is verifiably error-free at supply voltages down to 20O mV, achieving 1/625 the power-delay product of standard 5 V CMOS.
1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS
1-V power supply high-speed low-power digital circuit technology with 0.5-/spl mu/m multithreshold-voltage CMOS (MTCMOS) is proposed. This technology features both low-threshold voltage and