A 1-V 5-GHz Self-Bias Folded-Switch Mixer in 90-nm CMOS for WLAN Receiver

Abstract

A 5 GHz double balanced mixer (DBM) is implemented in standard 90 nm CMOS low-power technology. A novel low-voltage self-bias current reuse technique is proposed in the RF transconductance stage to obtain better third-order intermodulation intercept point (IIP ) and conversion gain (CG) when considering the process variations. The DBM achieves a CG of 12 dB, a noise figure (NF) of 10.6 dB and port-to-port isolations of better than 50 dB. The input second-order (IIP ) and IIP are 48 dBm and 4 dBm, respectively. Two I/Q DBMs are then integrated with a differential low-noise amplifier (DLNA) and a poly-phase filter, to from a direct-conversion receiver (DCR). The DCR achieves a CG of 26 dB with an NF of 2.7 dB at 21 mW power consumption from a 1 V supply voltage. The port-to-port isolations are better than 50 dB. The IIP and the IIP of the DCR are 33 dBm and dBm, respectively.

DOI: 10.1109/TCSI.2011.2173399

Cite this paper

@article{Chiou2012A15, title={A 1-V 5-GHz Self-Bias Folded-Switch Mixer in 90-nm CMOS for WLAN Receiver}, author={Hwann-Kaeo Chiou and Kuei-Cheng Lin and Wei-Hsien Chen and Ying-Zong Juang}, journal={IEEE Trans. on Circuits and Systems}, year={2012}, volume={59-I}, pages={1215-1227} }