A 1 TB/s 1 pJ/b 6.4 mm2/(TB/s) QDR Inductive-Coupling Interface Between 65-nm CMOS Logic and Emulated 100-nm DRAM

Abstract

1 TB/s 1 pJ/b 6.4 inductive-coupling interface between 65-nm complementary metal–oxide–semiconductor (CMOS) logic and emulated 100-nm dynamic random access memory (DRAM) is developed. operation is examined in 1024-bit parallel links. Compared to the latest wired 40-nm DRAM interface, the bandwidth is increased to 32 , and the energy consumption and the layout area are reduced to 1/8 and 1/22, respectively.

DOI: 10.1109/JETCAS.2012.2193836

Cite this paper

@article{Miura2012A1T, title={A 1 TB/s 1 pJ/b 6.4 mm2/(TB/s) QDR Inductive-Coupling Interface Between 65-nm CMOS Logic and Emulated 100-nm DRAM}, author={Noriyuki Miura and Mitsuko Saito and Tadahiro Kuroda}, journal={IEEE J. Emerg. Sel. Topics Circuits Syst.}, year={2012}, volume={2}, pages={249-256} }