A 1-GS/s 6-bit 6.7-mW ADC in 65-nm CMOS

@article{Yang2009A16,
  title={A 1-GS/s 6-bit 6.7-mW ADC in 65-nm CMOS},
  author={Jing Yang and Thura Lin Naing and Robert W. Brodersen},
  journal={2009 IEEE Custom Integrated Circuits Conference},
  year={2009},
  pages={287-290}
}
An asynchronous 6bit 1GS/s ADC is achieved by time interleaving two ADCs based on binary successive approximation algorithm (SA) using a capacitive ladder. The semi-close loop asynchronous technique eliminates the high internal clocks and significantly speeds up the SA algorithm. One bit redundancy is implemented to compensate the process variation of parasitic and the MOM capacitance. Fabricated in 65nm CMOS with an active area of 0.11mm2, it achieves a peak SNDR of 31.5dB at 1 GS/s sampling… CONTINUE READING

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