A 1 GS/s 6 Bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing

  title={A 1 GS/s 6 Bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing},
  author={Jing Yang and Thura Lin Naing and Robert W. Brodersen},
  journal={IEEE Journal of Solid-State Circuits},
An asynchronous 6 bit 1 GS/s ADC is achieved by time interleaving two ADCs based on the binary successive approximation (SA) algorithm using a series capacitive ladder. The semi-closed loop asynchronous technique eliminates the high internal clocks and significantly speeds up the SA algorithm. A key feature to reduce the power in this design involves relaxing the comparator requirements using an error correction technique, which can be viewed as an extension of the SA algorithm to remove… CONTINUE READING
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A 0.16 pJ/conversionstep 2.5 mW 1.25 GS/S 4b ADC in a 90 nm digital CMOS process

  • G. Van der Plas, S. Decoutere, S. Donnay
  • IEEE ISSCC Dig. Tech. Papers, Feb. 2006, p. 2310.
  • 2006
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