A 1 GHz portable digital delay-locked loop with infinite phase capture ranges

@article{Minami2000A1G,
  title={A 1 GHz portable digital delay-locked loop with infinite phase capture ranges},
  author={Kentarou Minami and Makoto Mizuno and Haruo Yamaguchi and Tatsuya Nakano and Yosuke Matsushima and Yasuaki Sumi and Tatsuhiro Sato and H. Yamashida and Masakazu Yamashina},
  journal={2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056)},
  year={2000},
  pages={350-351}
}
Delay-locked loops (DLLs) are widely used to align signal phases in many high-speed microprocessors and memories. Phase-locked loops (PLLs) are also used but their jitter is larger than that of DLLs, because DLLs have no jitter accumulation. However, conventional DLLs have design problems. One is that their phase capture ranges are limited, and another is that a special reset sequence is required. Dual DLL architectures are developed to overcome these problems. In these architectures, the… CONTINUE READING
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References

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Showing 1-4 of 4 references

A Portable Digital DLL for High-Speed CMOS Interface Circuits,

  • Garlepp, W B.
  • IEEE Journal of Solid-State Circuits,
  • 1999
1 Excerpt

A Semidigital Dual Delay-Locked Loop,

  • S. Sidropoulos, Mark A. Horowitz
  • IEEE Journal of Solid-State Circuits,
  • 1997
2 Excerpts

A Variable Delay Line PLL for CPU - Coprocessor Synchronization,

  • M. G. Johnson, E. L. Hudson
  • IEEE Journal of Solid-State Circuits,
  • 1988
2 Excerpts

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