A Sub-1.0V 20nm 5Gb/s/pin post-LPDDR3 I/O interface with Low Voltage-Swing Terminated Logic and adaptive calibration scheme for mobile application
- Young-Chul Cho, Yong-Cheol Bae
- Symposium on VLSI Circuits, 2013, pp. 240-241.
The demands on higher bandwidth with reduced power consumption in mobile market are driving mobile DRAM to have advanced design techniques. Proposed LPDDR4 in this paper achieves over 30% improved power efficiency and over 4.3Gbps data rate with 1.1V supply voltage. These are challenging target comparing with that of LPDDR3. This works includes various techniques including multi-channel per die, various trainings, low swing interface, DQS and clock frequency dividing, internal reference voltage for data and command-address signals and so on. This chip was fabricated in a 3-metal 2y-nm DRAM CMOS process.