A 1.1V 2y-nm 4.35Gb/s/pin 8Gb LPDDR4 mobile device with bandwidth improvement techniques

Abstract

The demands on higher bandwidth with reduced power consumption in mobile market are driving mobile DRAM to have advanced design techniques. Proposed LPDDR4 in this paper achieves over 30% improved power efficiency and over 4.3Gbps data rate with 1.1V supply voltage. These are challenging target comparing with that of LPDDR3. This works includes various techniques including multi-channel per die, various trainings, low swing interface, DQS and clock frequency dividing, internal reference voltage for data and command-address signals and so on. This chip was fabricated in a 3-metal 2y-nm DRAM CMOS process.

DOI: 10.1109/CICC.2014.6946032

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Cite this paper

@article{Song2014A12, title={A 1.1V 2y-nm 4.35Gb/s/pin 8Gb LPDDR4 mobile device with bandwidth improvement techniques}, author={Keunsoo Song and Sangkwon Lee and Dongkyun Kim and Youngbo Shim and Sangil Park and Bokrim Ko and Duckhwa Hong and Yongsuk Joo and Wooyoung Lee and Yongdeok Cho and Wooyeol Shin and Jaewoong Yun and Hyengouk Lee and Jeonghun Lee and Eunryeong Lee and Jaemo Yang and Hae-Kang Jung and Namkyu Jang and Joohwan Cho and Hyeongon Kim}, journal={Proceedings of the IEEE 2014 Custom Integrated Circuits Conference}, year={2014}, pages={1-4} }