A 1 . 8 Ghz-2 . 4 Ghz Fully Programmable Frequency Divider And A Dual-Modulus Prescaler For High Speed Frequency Operation In PLL System Using 250 nm Cmos Technology

@inproceedings{Joshi2012A1,
  title={A 1 . 8 Ghz-2 . 4 Ghz Fully Programmable Frequency Divider And A Dual-Modulus Prescaler For High Speed Frequency Operation In PLL System Using 250 nm Cmos Technology},
  author={Harsh Dipak Joshi and Sanjeev M. Ranjan},
  year={2012}
}
A Programmable Dual-modulus Prescaler and a fully programmable Frequency divider with 250nm are presented in this paper. The DualModulus prescaler includes a synchronous counter and a asynchronous counter. A high sped dynamic D-FF is used in cmos phase locked loops for GHz applications that reduce the power consumption. Dynamic D-FF is constructed using True single phase clock logic (TSPC).The maximum operating frequency varies between 1.8 GHz – 2.4 GHz with power consumption of 24mw at 2.5v… CONTINUE READING

References

Publications referenced by this paper.
SHOWING 1-10 OF 13 REFERENCES

Huang.2.4 ghz divide-by-256/271 single-ended frequency divider in standard 0.35-μm cmos technology

  • Sheng-Che Tseng, Chinchun Meng, Shao-Yu Li, Jen-Yi Su, Guo-Wei
  • In Microwave Conference Proceedings APMC Asian…
  • 2005

A 1.75 GHz/3-V Dual-Modulus divide by128/129 Prescaler in 0.7um CMOS

  • J.craninckx, M. Steyaert
  • IEEE J. of solid state circuits Vol 31, No. 7,PP…
  • 1996
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