A 0.9V 10-bit 100 MS/s switched-RC pipelined ADC without using a front-end S/H in 90nm CMOS


This paper presents a very low-voltage low-power pipelined ADC with 0.9-V supply voltage in a 90 nm CMOS process. A novel switched-RC sampling MDAC is proposed to obtain high linearity under very low-voltage and low-power conditions without significant degradation in speed or causing any reliability problem. Moreover, by eliminating S/H stage, power… (More)
DOI: 10.1109/ISCAS.2008.4541342


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