Corpus ID: 10014096

A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process

@article{Liu2009A01,
  title={A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process},
  author={Chun-Cheng Liu and S. Chang and Guan-Ying Huang and Yin-Zu Lin},
  journal={2009 Symposium on VLSI Circuits},
  year={2009},
  pages={236-237}
}
This paper reports a 10-bit 50MS/s SAR ADC with a set-and-down capacitor switching method. Compared to the conventional method, the average switching energy is reduced about 81%. At 50MS/s and 1.2V supply, the ADC consumes 0.92mW and achieves an SNDR of 52.78dB, resulting in an FOM of 52fJ/Conversion-step. Fabricated in a 0.13μm 1P8M CMOS technology, the ADC only occupies 0.075mm2 active area. 
View on IEEE
sscas.ee.ncku.edu.tw
88 Citations
Highly Influential Citations
8
Background Citations
37
Methods Citations
30
Results Citations
3

88 Citations

Citation Type

Citation Type

A 1V 11fJ/conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18µm CMOS
  • 103
  • PDF
A 1.8V 9bit 10MS/s SAR ADC in 0.18µm CMOS for bioimpedance analysis
0.5V 1OMS/S 9-Bits Asynchronous SAR ADC for BLE Receivers in L80NM CMOS Technology
A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS
  • Wen-Lan Wu, Yan Zhu, +5 authors R. Martins
  • Computer Science, Engineering
  • 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)
  • 2013
  • 9
  • PDF
A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS
  • 481
  • Highly Influenced
  • PDF
A 10-Bit, 50 MS/s, 55 fJ/conversion-step SAR ADC with split capacitor array
  • 1
A 10 b 1 MS / sto-10 MS / s 0 . 11 um CMOS SAR ADC for Analog TV Applications
  • 8
  • PDF
A 10b 1MS/s-to-10MS/s 0.11um CMOS SAR ADC for analog TV applications
  • 5
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure
  • 831
  • PDF
A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS
  • 18
...
1
2
3
4
5
...

References

SHOWING 1-7 OF 7 REFERENCES
A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS
  • J. Craninckx, G. V. D. Plas
  • Engineering, Computer Science
  • 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
  • 2007
  • 285
A 9.4-bit, 50-MS/s, 1.44-mW pipelined ADC using dynamic residue amplification
  • 33
A 8-bit 500-KS/s low power SAR ADC for bio-medical applications
  • 150
A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC Using Dynamic Source Follower Residue Amplification
  • 95
500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC
  • 296
  • PDF
An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS
  • 191
A 8-bit 500KS/s low power SAR ADC for bio-medical application,
  • IEEE Asian Solid-State Circuits Conference,
  • 2008