A 0.9 V 150 MHz 10 mW 4 mm/sup 2/ 2-D discrete cosine transform core processor with variable-threshold-voltage scheme

@article{Kuroda1996A0V,
  title={A 0.9 V 150 MHz 10 mW 4 mm/sup 2/ 2-D discrete cosine transform core processor with variable-threshold-voltage scheme},
  author={Tadahiro Kuroda and Tetsuya Fujita and Shinji Mita and T. Nagamatu and Shinichi Yoshioka and Fumihiko Sano and M. Norishima and Morimichi Murota and M. Kako and Masaaki Kinugawa and Masakazu Kakumu and Takayuki Sakurai},
  journal={1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC},
  year={1996},
  pages={166-167}
}
This two-dimensional 8/spl times/8 discrete cosine transform (DCT) core processor for portable multimedia equipment with HDTV-resolution in a 0.3 /spl mu/m CMOS triple-well double-metal technology operates at 150 MHz from a 0.9 V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3 V DCT. Circuit techniques for dynamically varying threshold voltage reduce active power dissipation with negligible overhead in speed, standby power and chip area. 
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