A 0.8V, sub-mW, varactor-tuning ring-oscillator-based clock generator in 32nm CMOS


A low-voltage operation, small-die-area, fully integrated Phase-Locked Loop (PLL) as a clock generator is described in an advanced 32nm CMOS technology. The PLL employs a fully digital, 6-bit automatic frequency calibrator (AFC), and varactors for frequency fine-tuning. To improve the performance and lower down the cost in mobile SoC applications, the PLL… (More)
DOI: 10.1109/ASSCC.2011.6123582


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