A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS

@article{Won2015A0W,
  title={A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS},
  author={Hyosup Won and Taehun Yoon and Jinho Han and Joon-Yeong Lee and Jong-Hyeok Yoon and Taeho Kim and Jeong-Sup Lee and Sangeun Lee and Kwangseok Han and Jinhee Lee and Jinho Park and Hyeon-Min Bae},
  journal={IEEE Journal of Solid-State Circuits},
  year={2015},
  volume={50},
  pages={399-413}
}
This paper describes a low-power 100 Gigabit Ethernet transceiver IC compliant with IEEE802.3ba 100GBASE-LR4 in 40 nm CMOS. The proposed bidirectional full-duplex transceiver IC contains a total of eight 28 Gb/s CDRs. Each CDR lane incorporates phase-rotator-based delay- and phase-locked loop (D/PLL) architecture for enhanced jitter filtering. All the CDR lanes operate independently while sharing a single voltage-controlled oscillator and supporting referenceless clock acquisition. To reduce… CONTINUE READING

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