A 0.8 ps DNL Time-to-Digital Converter With 250 MHz Event Rate in 65 nm CMOS for Time-Mode-Based $\Sigma \Delta$ Modulator

Abstract

A time-to-digital converter (TDC) is proposed to replace the multi-bit quantizer and the multi-bit feedback DAC of traditional voltage-mode ΣΔ modulator. Since time-mode systems process analog signals encoded in the time dimension rather than the voltage dimension, the proposed time-mode TDC makes the multi-bit ΣΔ ADC digital friendly and more suitable for… (More)
DOI: 10.1109/JSSC.2011.2156990

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