A 0.5V filter with PLL-based tuning in 0.18 /spl mu/m CMOS

  title={A 0.5V filter with PLL-based tuning in 0.18 /spl mu/m CMOS},
  author={Sujash S. Chatterjee and Y. Tsividis and P. R. Kinget},
  journal={ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.},
  pages={506-613 Vol. 1}
Design techniques that allow analog circuit operation with supply voltages as low as 0.5V are presented. A fully integrated 135kHz fifth-order elliptic LPF, including automatic bias circuits and an on-chip PLL for tuning, is implemented with standard devices in a 0.18 /spl mu/m CMOS process. The 1mm/sup 2/ chip has a measured DR of 57dB and draws 2.2mA from the 0.5V supply. 

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  • S. Chatterjee, Y. Tsividis
  • Kinget, “A 0.5-V Bulk-Input Fully Differential…
  • 2004
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