A 0.5-14-GHz 10.6-dB CMOS cascode distributed amplifier

@article{Liu2003A01,
  title={A 0.5-14-GHz 10.6-dB CMOS cascode distributed amplifier},
  author={Ren-Chieh Liu and Chin-Shen Lin and Kuo-Liang Deng and Huei Wang},
  journal={2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)},
  year={2003},
  pages={139-140}
}
A 0.5-14-GHz distributed amplifier (DA) using 0.18-/spl mu/m CMOS technology has been presented. It demonstrates the highest gain bandwidth product reported for a CMOS amplifier using a standard Si-based IC process. This DA chip achieves measured results of 10.6/spl plusmn/0.9 dB gain, NF between 3.4 and 5.4 dB with good return losses better than from 0.5 to 14 GHz. The measured output IP3 and P/sub ldB/ are +20 dBm and +10 dBm, respectively, from 2 to 10 GHz. 
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