A 0.46ps RJrms 5GHz wideband LC PLL for multi-protocol 10Gb/s SerDes

@article{Rao2009A0R,
  title={A 0.46ps RJrms 5GHz wideband LC PLL for multi-protocol 10Gb/s SerDes},
  author={Chethan Rao and Alvin Wang and Shaishav Desai},
  journal={2009 IEEE Custom Integrated Circuits Conference},
  year={2009},
  pages={239-242}
}
A 2.3 to 5GHz LC PLL is implemented in 65nm standard CMOS for 0.6 to 10Gb/s SerDes applications. The LC VCO is measured to have 67% coarse tuning range and worst-case hold range of 9.6%. The rms random jitter (RJrms) on the TX output with a clock pattern is measured to be 460fs at 5GHz and 548fs at 3.125GHz. The total power dissipated from the 1.8V, 1.0V supplies is 29mW at 5GHz. 
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