A 0.4–1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit

Abstract

A 0.4-1.6GHz spur-free bang-bang PLL (BBPLL) is demonstrated in a 65nm CMOS process where a standard D-flip/flop (DFF) based frequency subtractor is used in lieu of a conventional divider, for down-converting the feedback clock frequency. The inherent first-order noise-shaping property allows the proposed frequency subtraction circuit to mitigate spur-noise… (More)
DOI: 10.1109/VLSIC.2015.7231355
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