A 0.3-V 0.705-fJ/Conversion-Step 10-bit SAR ADC With a Shifted Monotonic Switching Procedure in 90-nm CMOS

@article{Hsieh2016A00,
  title={A 0.3-V 0.705-fJ/Conversion-Step 10-bit SAR ADC With a Shifted Monotonic Switching Procedure in 90-nm CMOS},
  author={Sung-En Hsieh and Chih-Cheng Hsieh},
  journal={IEEE Transactions on Circuits and Systems II: Express Briefs},
  year={2016},
  volume={63},
  pages={1171-1175}
}
This brief presents a 0.3-V energy-efficient 10-bit successive approximation register analog-to-digital converter. A shifted monotonic switching procedure is proposed to achieve an average digital-to-analog converter switching energy of 63.75 CV2. Two redundant bits are implemented with error tolerance of ±12 mV for dynamic comparator offset and common-mode reference (Vcm) sensitivity. The prototype is designed and fabricated in a 90-nm CMOS with a core size of 250 μm × 50 μm (0.0125 mm2). At… CONTINUE READING

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