A 0.039um2 high performance eDRAM cell based on 32nm High-K/Metal SOI technology

  title={A 0.039um2 high performance eDRAM cell based on 32nm High-K/Metal SOI technology},
  author={Neelam Butt and Kevin McStay and Alberto Cestero and H. Ho and Weixin Kong and Shuo Fang and Rishikesh Krishnan and B. Khan and Alex Tessier and William D. Davies and Seung C. Lee and Y. Zhang and J. B. Johnson and S. Rombawa and Rohit S. Takalkar and Alisa Blauberg and K. V. Hawkins and Jin Shan Liu and Sami Rosenblatt and Pratibha Goyal and Sonali Gupta and Jared Ervin and Zhengwen Li and S. Galis and J. Barth and Ming Yin and Tom Weaver and Jinghong Li and Shreesh Narasimha and P. Parries and W. Kirklen Henson and Norman Robson and Toshiaki Kirihata and Michael P. Chudzik and E. Maciejewski and Paul D. Agnello and Scott R. Stiffler and S. S. Iyer},
  journal={2010 International Electron Devices Meeting},
We present industry's smallest eDRAM cell and the densest embedded memory integrated into the highest performance 32nm High-K Metal Gate (HKMG) SOI based logic technology. The cell is aggressively scaled at 58% (vs. 45nm) and features the key innovation of High-K Metal (HK/M) stack in the Deep Trench (DT) capacitor. This has enabled 25% higher capacitance and 70% lower resistance compared to conventional SiON/Poly stack at matched leakage and reliability. The HKMG access transistor developed in… CONTINUE READING
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Top-Down image of 32nm eDRAM array. Table 1 Some of the key elements for eDRAM array design

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