A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS

@article{Yin2012A0M,
  title={A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS},
  author={Guohe Yin and He-Gong Wei and U. Fat Chio and Sai-Weng Sin and U Seng-Pan and Zhihua Wang and Rui Paulo Martins},
  journal={2012 Proceedings of the ESSCIRC (ESSCIRC)},
  year={2012},
  pages={377-380}
}
This paper presents a Successive Approximation Register Analog-to-Digital Converter (SAR ADC) design for sensor applications. An energy-saving switching technique is proposed to achieve ultra low power consumption. The measured Signal-to-Noise-and-Distortion Ratio (SNDR) of the ADC is 58.4 dB at 2 MS/s with an ultra-low power consumption of only 6.6 μW from a 0.8V supply, resulting in a Figure-Of-Merit (FOM) of 4.9 fJ/conversion-step. The prototype is fabricated in 65 nm CMOS technology with an… CONTINUE READING

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