A 0.02-mm$^{2}$ 9-Bit 50-MS/s Cyclic ADC in 90-nm Digital CMOS Technology

@article{Huang2010A0,
  title={A 0.02-mm\$^\{2\}\$  9-Bit 50-MS/s Cyclic ADC in 90-nm Digital CMOS Technology},
  author={Yen-Chuan Huang and Tai-Cheng Lee},
  journal={IEEE Journal of Solid-State Circuits},
  year={2010},
  volume={45},
  pages={610-619}
}
A 9-bit cyclic ADC employs a track-and-evaluation technique for enhancing the speed of residue evaluation. The proposed multiply-by-two circuit has a shorter evaluation time than the conventional design due to the application of a partial positive feedback topology. The residue evaluation and sampling phases are merged to reduce the conversion latency. Hence, only four clock cycles are required to perform the 9-bit conversion. The proposed 0.02-mm2 ADC has been fabricated in 90-nm digital CMOS… CONTINUE READING

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