- A 0 . 8pm CMOS 2 . 5 Gb / s Oversampling Receiver and Transmitter for Serial Links

@inproceedings{Yang1999A0,
  title={- A 0 . 8pm CMOS 2 . 5 Gb / s Oversampling Receiver and Transmitter for Serial Links},
  author={Chih-Kong Ken Yang and Horowitz},
  year={1999}
}
A receiver targeting OC-48 (2.488Gbps) serial data link has been designed and integrated in a 0.8μm CMOS process. An experimental receiving front end circuit demonstrates the viability of using multiple phased clocks to overcome the intrinsic gatespeed limitations in the demultiplexing (receiving) and multiplexing (transmitting) of serial data. To perform clock recovery, data is 3x oversampled so that transitions can be detected to determine bit boundaries. The design of a transmitter for the… CONTINUE READING
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