A (64,45) Triple Error Correction Code for Memory Applications

  title={A (64,45) Triple Error Correction Code for Memory Applications},
  author={Pedro Reviriego and M. F. Flanagan and J. A. Maestro},
  journal={IEEE Transactions on Device and Materials Reliability},
Memories are commonly protected with error correction codes to avoid data corruption when a soft error occurs. Traditionally, per-word single error correction (SEC) codes are used. This is because they are simple to implement and provide low latency. More advanced codes have been considered, but their main drawback is the complexity of the decoders and the added latency. Recently, the use of one-step majority logic decodable codes has been proposed for memory protection. One-step majority logic… CONTINUE READING
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Error Control Coding, 2nd ed

  • S. Lin, D. J. Costello
  • Englewood Cliffs, NJ: Prentice-Hall,
  • 2004
Highly Influential
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Multi-bit error correction methods for latency-constrained flash memory systems

  • P. Ankolekar, S. Rosner, R. Isaac, J. Bredow
  • IEEE Trans. Device Mater. Rel., vol. 10, no. 1…
  • 2010
1 Excerpt

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