8T Single-ended sub-threshold SRAM with cross-point data-aware write operation

@article{Chiu20118TSS,
  title={8T Single-ended sub-threshold SRAM with cross-point data-aware write operation},
  author={Yi-Wei Chiu and Jihi-Yu Lin and Ming-Hsien Tu and Shyh-Jye Jou and Ching-Te Chuang},
  journal={IEEE/ACM International Symposium on Low Power Electronics and Design},
  year={2011},
  pages={169-174}
}
This paper presents a new 8T SRAM cell with data-aware cross-point Write operation and series connected Read buffer for low power and low voltage operation. The cell features a shared footer device to control the VGND for cell pass-gate (Write) transistors and the Read buffer. The row-based VGND control and the column-based data-aware Write Word-Line form a cross-point Write structure, thus eliminating Write Half-Select Disturb to facilitate bit-interleaving architecture. Replica based timing… CONTINUE READING
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