8.4 A 2.5ps 0.8-to-3.2GHz bang-bang phase- and frequency-detector-based all-digital PLL with noise self-adjustment

@article{Jang201784A2,
  title={8.4 A 2.5ps 0.8-to-3.2GHz bang-bang phase- and frequency-detector-based all-digital PLL with noise self-adjustment},
  author={Tae-Kwang Jang and Seokhyeon Jeong and Dongsuk Jeon and Kyojin David Choo and Dennis Sylvester and David Blaauw},
  journal={2017 IEEE International Solid-State Circuits Conference (ISSCC)},
  year={2017},
  pages={148-149}
}
Digital PLLs are popular for on-chip clock generation due to their small size and technology portability. Variability tolerance is a key design challenge when designing such PLLs in an advanced CMOS technology. Environmental variations, such as mismatch, process, supply voltage, and temperature (PVT) perturb device characteristics and result in performance… CONTINUE READING