8-mW, 1-V, 100-Msps, 6-bit A/D converter using a transconductance latched comparator

@article{Terada20008mW11,
  title={8-mW, 1-V, 100-Msps, 6-bit A/D converter using a transconductance latched comparator},
  author={J. Terada and Y. Matsuya and Fumiharu Morisawa and Y. Kado},
  journal={Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)},
  year={2000},
  pages={53-56}
}
  • J. Terada, Y. Matsuya, +1 author Y. Kado
  • Published 2000
  • Engineering
  • Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)
A very low-power, high-speed flash A/D converter front-end composed of a new transconductance latched comparator was developed. We established a butterfly sorting technique to guarantee the monotonicity of the converter. The 6-bit A/D front-end achieves a speed of 100 Msps and dynamic range of 33 dB with power consumption of only 7 mW at 1 V and the butterfly sorter guarantees 6-bit monotonicity with an extra power consumption of 1 mW. 

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