7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture

@article{Noguchi201575A3,
  title={7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture},
  author={Hiroki Noguchi and Kazutaka Ikegami and Keiichi Kushida and Keiko Abe and Shogo Itai and Satoshi Takaya and Naoharu Shimomura and Junichi Ito and Atsushi Kawasumi and Hiroyuki Hara and Shinobu Fujita},
  journal={2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers},
  year={2015},
  pages={1-3}
}
Nonvolatile memory, spin-transfer torque magnetoresistive RAM (STT-MRAM) is being developed to realize nonvolatile working memory because it provides high-speed accesses, high endurance, and CMOS-logic compatibility. Furthermore, programming current has been reduced drastically by developing the advanced perpendicular STT-MRAM [1]. Several-megabit STT-MRAM with sub-5ns operation is demonstrated in [2]. Advanced perpendicular STT-MRAM achieve ~3× power saving by reducing leakage current in… CONTINUE READING
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Fine-grain power-gating on STT-MRAM peripheral circuits with locality-aware access control,” Memory Forum (in conjunction with ISCA)

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