65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS

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@inproceedings{Yamaoka200865nmLH, title={65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS}, author={Masanao Yamaoka and Noriaki Maeda and Yasuhisa Shimazaki and Kenichi Osada}, booktitle={ISSCC}, year={2008} }