64-bit and multimedia extensions in the PA-RISC 2.0 architecture

@article{Lee199664bitAM,
  title={64-bit and multimedia extensions in the PA-RISC 2.0 architecture},
  author={Ruby B. Lee and Jerome C. Huck},
  journal={COMPCON '96. Technologies for the Information Superhighway Digest of Papers},
  year={1996},
  pages={152-160}
}
  • Ruby B. Lee, Jerome C. Huck
  • Published 25 February 1996
  • Computer Science
  • COMPCON '96. Technologies for the Information Superhighway Digest of Papers
This paper describes the architectural extensions to the PA-RISC 1.1 architecture to enable 64-bit processing of integers and pointers. It also describes MAX, the Multi-media Acceleration eXtensions which speed up the processing of multimedia and other applications with parallelism at the intra instruction, or subword, level. Other additions to the PA-RISC 2.0 architecture include performance enhancements with respect to memory hierarchy management, branch penalty reduction, and floating-point… 
Multimedia extensions for general-purpose processors
  • Ruby B. Lee
  • Computer Science
    1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing
  • 1997
This paper gives an overview of the multimedia instructions that have been added to the instruction set architectures of general-purpose microprocessors to accelerate media processing. Examples are
MMX technology extension to the Intel architecture
TLDR
MMX technology extends the Intel architecture to improve the performance of multimedia, communications, and other numeric-intensive applications by introducing data types and instructions to the IA that exploit the parallelism in these applications.
A 2 way VLIW processor architecture for embedded multimedia applications
TLDR
This processor has a 2-issue VLIW architecture with 64-bit SIMD arithmetic functional units to exploit the instruction-level and subword data parallelism found in multimedia applications and shows a comparable or higher performance when compared to the 8-issue TMS320C62xx.
Mapping of application software to the multimedia instructions of general-purpose microprocessors
TLDR
The paper examines some typical multimedia kernels, like block match, matrix transpose, box filter and the IDCT, coded with and without the MAX2 instructions, to illustrate programming techniques for exploiting subword parallelism and superscalar instruction parallelism.
Mid-range and high-end PA-RISC computer systems
  • Roy Elsbernd
  • Computer Science
    COMPCON '96. Technologies for the Information Superhighway Digest of Papers
  • 1996
TLDR
The architecture of the new Mohawk product within the Hawks family of products is described, which uses the PA-8000 processor and the "Hawks" hardware platform to provide a high performance mid-range server system.
Design and implementation of a Multimedia Extension for a RISC Processor
TLDR
This work focuses on the MIPS microarchitecture because it follows the RISC (Reduced Instruction Set Computer) philosophy quite closely, which is desirable since it simplifies implementation and it is easy to understand by students.
Subword parallelism with MAX-2
TLDR
It is proposed that subword parallelism-parallel computation on lower precision data packed into a word-is an efficient and effective solution for accelerating media processing.
Intel Israel Design Center Designed to accelerate multimedia and communications software , iz ' lillx tech nology impmues performance
applications. MX technology extends the Intel architecture (IA) to improve the performance of multimedia, communications, and other numeric-intensive applications. It uses a SIMD (single-instruction,
Architecture and compiler design issues in programmable media processors
TLDR
A speculative run-time technique for data parallelism that executes loop iterations in parallel across a multi-clustered architecture is proposed and provides architecture support for identifying and recovering from misspeculations.
CoMPARE: A Simple Reconfigurable Processor Architecture Exploiting Instruction Level Parallelism
TLDR
CoMPARE uses an LUT-based recon-gurable logic array as an extension to a conventional ALU to build special instructions for acceleration of diierent applications to maintain the common programming model for microprocessors.
...
1
2
3
4
5
...

References

SHOWING 1-10 OF 11 REFERENCES
Advanced performance features of the 64-bit PA-8000
  • Doug Hunt
  • Computer Science
    Digest of Papers. COMPCON'95. Technologies for the Information Superhighway
  • 1995
The PA-8000 is Hewlett-Packard's first CPU to implement the new 64-bit PA2.0 architecture. It combines a high clock frequency with a number of advanced microarchitectural features to deliver
Accelerating multimedia with enhanced microprocessors
TLDR
A software video decoder attains MPEG video and audio decompression and playback at real-time rates of 30 frames per second, on an entry-level workstation, with general-purpose parallel subword instructions that can accelerate a variety of multimedia programs.
Pathlength reduction features in the PA-RISC architecture
TLDR
A description is given of representative pathlength reduction features of PA-RISC (reduced instruction set computer) instructions in memory accessing, functional operations, and instruction sequencing, and comparison is made with the MIPS instruction set.
Precision architecture
The processor component of the Hewlett-Packard Precision Architecture system is described. The architecture's goals, how the architecture addresses the spectrum of general-purpose user information
1 Architecture and Instruction Set Reference Manual, 3rd edition, Part Number 09740-90039
  • 1 Architecture and Instruction Set Reference Manual, 3rd edition, Part Number 09740-90039
  • 1994
1 Architecture and Instruction Set Reference Manual, 2nd. edition, Part Number 09740-90039
  • 1 Architecture and Instruction Set Reference Manual, 2nd. edition, Part Number 09740-90039
  • 1992
1 Architecture and Instruction Set Reference Manual, 1st. edition, Part Number 09740-90039
  • 1 Architecture and Instruction Set Reference Manual, 1st. edition, Part Number 09740-90039
  • 1990
Hewlett-Packard Precision Architecture: The Processor
  • Hewlett-Packard Journal
  • 1986
Multimedia Acceleration with Subword Parallelism in Microprocessors
  • Distinguished Lecture Series X
  • 1995
...
1
2
...