6.9 A 1.1µm 33Mpixel 240fps 3D-stacked CMOS image sensor with 3-stage cyclic-based analog-to-digital converters

@article{Arai201669A1,
  title={6.9 A 1.1µm 33Mpixel 240fps 3D-stacked CMOS image sensor with 3-stage cyclic-based analog-to-digital converters},
  author={Toshiki Arai and Toshio Yasue and Kazuya Kitamura and Hiroshi Shimamoto and Tomohiko Kosugi and Sung-Wook Jun and Satoshi Aoyama and Ming-Chieh Hsu and Yuichiro Yamashita and Hirofumi Sumi and Shoji Kawahito},
  journal={2016 IEEE International Solid-State Circuits Conference (ISSCC)},
  year={2016},
  pages={126-128}
}
There is an increasing demand for high-reality video systems. The ITU-R has standardized video parameters for ultra-high-definition TV (UHDTV), and the full-specification video signal stated in this international standard is prescribed as having a 7,680 (H) × 4,320 (V) pixel count, 120Hz frame frequency with progressive scanning, 12b tone reproduction, and wide color gamut. A 33Mpixel 120fps CMOS image sensor with a 12b column-parallel analog-to-digital converter (ADC) is reported in [1]. In… CONTINUE READING
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2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers • 2015
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