6.7 A 1.2e− temporal noise 3D-stacked CMOS image sensor with comparator-based multiple-sampling PGA

@article{Shiraishi201667A1,
  title={6.7 A 1.2e− temporal noise 3D-stacked CMOS image sensor with comparator-based multiple-sampling PGA},
  author={Kei Shiraishi and Yasuhiro Shinozuka and Tomonori Yamashita and Kazuhide Sugiura and Naoto Watanabe and Ryuta Okamoto and Tatsuji Ashitani and Masanori Furuta and Tetsuro Itakura},
  journal={2016 IEEE International Solid-State Circuits Conference (ISSCC)},
  year={2016},
  pages={122-123}
}
This paper presents a 1.2e-, 3D-stacked CMOS image sensor (CIS) for mobile applications. A key motivation for using a stacked configuration is to minimize the chip area. Also, since numerous components must be integrated into the bottom chip, a scaled 65nm CMOS process is adopted for the bottom chip. The developed CIS features 1.2e- temporal noise with extremely high power efficiency by employing a multiple-sampling (MS) technique. A 2nd-order incremental ΔΣ ADC with inverter-based switched… CONTINUE READING