6-b 1.6-GS/s flash ADC with distributed track-and-hold pre-comparators in a 0.18µm CMOS

@article{Chen20096b1F,
  title={6-b 1.6-GS/s flash ADC with distributed track-and-hold pre-comparators in a 0.18µm CMOS},
  author={Chun-Chieh Chen and Yu-Lun Chung and C H Chiu},
  journal={2009 International Symposium on Signals, Circuits and Systems},
  year={2009},
  pages={1-4}
}
This work presents a novel flash analog-to-digital converter (ADC) with distributed track-and-hold pre-comparators (THPCs). Utilizing the proposed architecture, the loading capacitances of the ADC front-end sampling sub-circuits can be markedly reduced, thereby improving operation speed. In a standard 0.18µm CMOS process, a 1.6GS/s 6-bit flash ADC is implemented to demonstrate the feasibility of the proposed distributed THPC architecture. The equivalent input capacitance of each input port of… CONTINUE READING

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