5T SRAM With Asymmetric Sizing for Improved Read Stability

@article{Nalam20115TSW,
  title={5T SRAM With Asymmetric Sizing for Improved Read Stability},
  author={Satyanand Nalam and Benton H. Calhoun},
  journal={IEEE Journal of Solid-State Circuits},
  year={2011},
  volume={46},
  pages={2431-2442}
}
Conventional 6-transistor (6T) SRAM scaling to newer technologies and lower supply voltages is difficult due to a complex trade-off space involving stability, performance, power, and area. Local and global variation make SRAM design even more challenging. We present a 5-transistor (5T) bitcell that uses sizing asymmetry to improve read stability and to provide an efficient knob for trading off the aforementioned metrics. In this paper, we compare the 5T with the conventional 6T and the 8T and… CONTINUE READING
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