55-mW 1.2-V 12-bit 100-MSPS Pipeline ADCs for Wireless Receivers

@article{Ito200655mW11,
  title={55-mW 1.2-V 12-bit 100-MSPS Pipeline ADCs for Wireless Receivers},
  author={Tomohiko Ito and Daisuke Kurose and Takeshi Ueno and Takafumi Yamaji and Tetsuro Itakura},
  journal={2006 Proceedings of the 32nd European Solid-State Circuits Conference},
  year={2006},
  pages={540-543}
}
For wireless receivers, low-power 1.2-V 12-bit 100-MSPS pipeline ADCs are fabricated in 90-nm CMOS technology. To achieve low-power dissipation at 1.2 V without the degradation of SNR, the configuration of 2.5bit/stage is employed with an I/Q amplifier sharing technique. Furthermore, single-stage common-source amplifiers are used in a sample-and-hold (S/H) circuit and a 1st multiplying digital-to-analog converter (MDAC). The common-source amplifier with two-stage transimpedance gain-boosting… CONTINUE READING
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