500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC

@article{Ginsburg2007500MSs5A,
  title={500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC},
  author={B. P. Ginsburg and A. P. Chandrakasan},
  journal={IEEE Journal of Solid-State Circuits},
  year={2007},
  volume={42},
  pages={739-747}
}
A 500-MS/s 5-bit ADC for UWB applications has been fabricated in a 65-nm CMOS technology using no analog-specific processing options. The time-interleaved successive approximation register (SAR) architecture has been chosen due to its simplicity versus flash and its amenability to scaled technologies versus pipelined, which relies on operational amplifiers. Six time-interleaved channels are used, sharing a single clock operating at the composite sampling rate. Each channel has a split capacitor… CONTINUE READING
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