42% power savings through glitch-reducing clocking strategy in a hearing aid application

@article{Carbognani200642PS,
  title={42% power savings through glitch-reducing clocking strategy in a hearing aid application},
  author={Flavio Carbognani and Felix B{\"u}rgin and Norbert Felber and Hubert Kaeslin and Wolfgang Fichtner},
  journal={2006 IEEE International Symposium on Circuits and Systems},
  year={2006},
  pages={4 pp.-}
}
Glitches are responsible for a significant proportion of overall power dissipation in digital signal processing circuits. Activity-reduction techniques that involve an optimized clocking strategy have been applied to a front-end block in a DSP adaptive directional microphone for hearing aids. Functionally equivalent implementations, differing only in their clocking scheme, have been integrated on silicon in a 0.25 mum CMOS technology. Measurements and post-layout simulations confirm a 42… CONTINUE READING

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ml 1 ; l _ 1 l _ l 1 l ; 1 ; 1 ; l _ " Two - phase clocking and a new latch design for low - power portable applications , " in Proc . Power and Timing Modeling , Optimization and Fig . 7

  • F. Buergin, N. Felber, H. Kaeslin, W. Fichtner

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