40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist


This paper presents a new bit-interleaving 12T subthreshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to improve the Write-ability to mitigate increased device variations at low supply voltage under deep sub-100 nm processes. The disturb-free feature facilitates the bit-interleaving architecture that can reduce multiple-bit errors in a… (More)
DOI: 10.1109/TCSI.2014.2332267


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